There is a current interest in CMOS active pixel sensor imagers for use as low cost imaging devices. FIG. 1 shows a signal processing system 100 that includes a CMOS active pixel sensor (“APS”) pixel array 230 and a controller 232 that provides timing and control signals to enable the read out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M×N pixels, with the size of the array 230 depending on a particular application. The imager pixels are readout a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Signals stored in the selected row of pixels are provided on column lines to a readout circuit 242. The pixel signals read from each of the columns are then readout sequentially using a column addressing circuit 244.
FIG. 2 shows the pixel array 230 of the system 100 of FIG. 1 in greater detail. FIG. 2 illustrates a six transistor (6T) CMOS pixel cell 10 in the pixel array 230. The 6T CMOS pixel cell 10 generally comprises a photo-conversion device 23 for generating and collecting charge generated by light incident on the pixel cell 10, and a transfer transistor 27 for transferring charge from the photo-conversion device 23 to a sensing node, typically a floating diffusion region 5. The floating diffusion region 5 is electrically connected to the gate of an output source follower transistor 19. The pixel cell 10 also includes a reset transistor 16 for resetting the floating diffusion region 5 to a predetermined voltage (shown as the array pixel supply voltage Vaa_pix); and a row select transistor 18 for outputting a signal from the source follower transistor 19 to an output column line in response to a row select signal. Although not required, in this exemplary pixel cell 10, a capacitor 20 may also be included to increase the charge storage capacity of floating diffusion region 5. One plate of the capacitor 20 is coupled to Vaa_pix and the other plate of the capacitor 20 is coupled to the floating diffusion region 5 through a dual conversion gain (“DCG”) transistor 21. Although also not required, in this exemplary pixel 10, a high dynamic range (“HDR”) transistor 25 is included. One source/drain of HDR transistor 25 is coupled to Vaa_pix and the other source/drain of the HDR transistor 25 is coupled to the photo-conversion device 23.
In the CMOS pixel cell 10 depicted in FIG. 2, electrons are generated by light incident on the photo-conversion device 23. These charges are transferred to the floating diffusion region 5 by the transfer transistor 27 when the transfer transistor 27 is activated. The source follower transistor 19 produces an output signal based on the transferred charges. The output signal is proportional to the number of electrons extracted from the photo-conversion device 23. When DCG transistor 21 is enabled, capacitor 20 is coupled to the floating diffusion region 5 and increases the storage capability and charges the conversion gain of floating diffusion region 5. When HDR transistor 25 is enabled, Vaa_pix is coupled to the photo-conversion device 23 and drives some charges away from the photo conversion device 23 which increases the dynamic range of pixel cell 10.
It is desirable to increase the fill factor and charge storage capacity of the pixels 10 in the array 230. However, the inclusion of a capacitor 20 and DCG transistor 21 and the control lines to control them requires space in the pixel 10 and/or in the array 230. Additionally, the HDR transistor 25 (to increase the dynamic range) requires space in the pixel 10 and/or in the array 230. There is a tradeoff of space: the greater space consumed by capacitors and the transistors, the less space available for the photo-conversion device 23. As such, including capacitors and transistors and the control lines to control them in the array 230 affects the fill factor of the array 230. Therefore, it is desirable to include controllable capacitors and transistors to increase charge storage capacity and dynamic range without significantly effecting the fill factor of the array 230.